The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. Since WiGig transceivers use carrier frequencies in the range of 60 GHz, parasitic capacitance can transfer these high frequency signals into other circuit components of the system design causing undesirable effects, particularly through substrate coupling. These effects can impact the performance and behavior of receiver and transmitter units. These parasitic capacitances are carefully monitored and are minimized, if possible, to reduce these undesirable effects.
CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel devices and P-channel devices (MOS device) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS devices. Current channel lengths examples are 40 nm, the power supply of VDD equals 1.2V and the number of layers of metal levels can be 8 or more. This technology typically scales with technology.
CMOS technology delivers a designer with the ability to form very large system level design on one die known as a System On a Chip (SOC). The SOC are complex systems with millions, if not billions, of transistors which contain analog circuits and digital circuits. The analog circuits operate purely analog, the digital circuits operate purely digital and these two circuits types can be combined together to form circuits operating in a mixed-signal.
For example, digital circuits in their basic form only use digital logic and some examples can be a component comprising at least one; processor, memory, control logic, digital I/O circuit, reconfigurable logic and/or hardware programmed that to operate as hardware emulator. Analog circuits in their basic form only use only analog circuits and some examples can be a component comprising at least one; amplifier, oscillator, mixer, and/or filter. Mixed signal in their basic form only use both digital and analog circuits and some examples can be a component comprising at least one: DAC (Digital to Analog Convertor), Analog to Digital Converter (ADC), Power Supply control, Phase Lock Loop (PLL), and/or device behavior control over Process, Voltage and Temperature (PVT). The combination of digital logic components with analog circuit components can appear to behave like mixed signal circuits; furthermore, these examples that have been provided are not exhaustive as one knowledgeable in the arts understands.
The SOC can generate a large amount of switching noise that couples through parasitic reactances formed in the die and between metal layers and could become a hostile environment for critical analog circuits. Analog designers attempt to minimize this form of noise coupling using any know means in the art, if possible. Such noise coupling, for example, can influence the operation of two or more oscillators to phase lock together even though the desired intent was to maintain a frequency difference between the two oscillators on the die.
Transceivers comprise at least one transmitter and at least one receiver and are used to interface to other transceivers in a communication system. One version of the transmitter can comprise at least one of each: DAC, LPF (Low Pass Filter), mixer, local oscillator, power amplifier and interface port that are coupled forming a RF (Radio Frequency) transmit chain. One version of the receiver can comprise at least one of each: interface port, LNA (Low Noise Amplifier), mixer, BB (Base Band) amplifier, LPF and ADC that are coupled forming a RF receive chain. The interface port can be shared between the two chains. In other situations, at least one interface port can be associated with each chain. Furthermore, each RF transmit and receive chains can operate on an in-phase (I) signal and the quadrature-phase (Q) signal simultaneously. Both RF transmit and RF receive chains can comprise other components known in the art to interface to other transceivers; they can be a homodyne system, heterodyne system, or a low IF system. Although the interface port is shown as an antenna; the interface port can be a transmission line, a transformer interface, or any means of interfacing to other transceivers. The transmit and receive chains are usually coupled to a block that performs baseband operations.
One of the critical design parameters of a transceiver occurs between the in-phase (I) and the quadrature-phase (Q) signals in the transmit and receive chains. Ideally, the amplitude of and phase difference between these (In-phase/Quadrature Phase) I/Q signals must remain constant with a 90° separation over a range of frequencies. However, due to mismatches between fabricated devices, process variations, temperature changes, voltage variations, layout structures, adjacent layout structures and their parasitic reactances etc., maintaining the same amplitude and 90° phase difference over the desired range of operating frequencies is a challenging task. Various methods and circuits as are well known in the art can be used to minimize the amplitude variations and maintain nearly a 90° phase separation between the I/Q signals over the operating range of frequencies.
Often, these methods and circuits to maintain the amplitudes constant and maintain nearly a 90° phase separation between the I/Q signals over the operating range of frequencies increase the use of die area (a valuable commodity in a chip), increase the use of analog and/or digital circuits (causing an increase in overall power dissipation), and thereby adding complexity to the overall transceiver. Incorporating these techniques into the design causes shortcomings, such as, the chip cost to increase, shorter battery life (particularly for portable wireless handheld units) and potentially slower operating behavior (due to added circuits). In addition, the transceiver requires the minimization of LO (Local Oscillator) leakage and requires the LPFs in the transmit and receive chains to have a specific bandwidth. It would be very desirable to overcome these shortcomings, achieving a smaller die, lower power dissipation and faster performance, yet still minimize the amplitude variations and maintain nearly a 90° phase separation between the I/Q signals, control the bandwidth of the LPFs and LO leakage over the operating range of frequencies.